In recent years, design rules are increasingly scaled down to meat with the increase in the integration of LSI (large scale integration) and need for high speed signal transmission, and this resulted in the accelerated decrease of the pitch and width of the interconnections and distance between the interconnections. Multi-layer interconnections have also been used to correspond to the need of the high shrinkage of the semiconductor device. The shrinkage and high integrity of the interconnection circuit, however, were associated with an increased electrical resistivity of the interconnection, and since this increase in the interconnection resistance invited slowing of the signal transmission, various attempts are recently made to use an interconnection having a lower electric resistance. One such attempt is use of a Cu based alloy in forming a Cu based alloy interconnection since Cu based alloy interconnection can reduce the electric resistance to a level lower than that of the conventional Al based alloy interconnection.
Damascene process technology has been used in fabricating the multilayer structure of the Cu based interconnection (for example, see Patent Document 1). This method is accomplished by an insulator film of silicon oxide, silicon nitride, or the like on the semiconductor substrate by the method commonly used in the art; forming an interconnection trench or an interlayer connection hole such as a trench or a via hole for embedding the interconnection in the insulator film; depositing a TaN thin film on the interior surface of such trench or the like; forming a seed layer of the Cu thin film; and filling the Cu thin film in the trench or the via hole; and removing the unnecessary interconnection material that has deposited on the part other than the trench or the via hole by chemical mechanical polishing (CMP) to thereby leave the interconnection material only in the interior of the trench or the via hole for use as the interconnection.
In spite of the shrinkage of the LSI interconnection according to the road map, and the resulting decrease in the width of the trench and the diameter of the via hole together with the increase in the aspect ratio (ratio of the pore depth to the pore groove diameter), filling of the metal in such minute groove by conventional electroplating suffered from the technical limit in the filling the metal in the minute groove, and complete filling of the metal in the minute via having a high aspect ratio or the via and the narrow trench having an interconnection width of up to 100 nm has been difficult.
In addition to the complete filling in the groove, the Cu based alloy interconnection is also required to have properties such as low electric resistance (ρ≦3.0 μΩcm), connection reliability (formation of a reliable contact), and interconnection reliability (resistance to disconnection by stress migration (SM resistance), resistance to disconnection by electromigration (EM resistance), etc.). In order to increase the reliabilities as described above, use of the Cu based alloy interconnection is contemplated in a high performance ULSI device. However, thin films of Cu alloy are difficult to form by electroplating, and a thin film of Cu alloy fulfilling all of such properties is quite difficult to realize.
While formation of the Cu based alloy interconnection by the damascene process is associated with the difficulties as described above, such Cu based alloy interconnection formed by damascene process is finding a wider use in Japan particularly in customer specific IC due to the economic advantage, and the damascene process is conceived to be continuously used as a process of forming the Cu based alloy interconnection. Accordingly, there is a need to develop a technology which can form a Cu based alloy interconnection having a low electric resistance, a high connection reliability, and a high interconnection reliability by the damascene process.
One method that has been proposed as a way to realize complete filling of the Cu based metal in the trench or the via hole is the formation of the Cu based alloy interconnection by CVD (chemical vapor deposition). Such formation of a film by CVD, however, is associated with the problems such as difficulty of forming a film of high purity as well as high cost.
One method effective in solving the problems associated with the electroplating or the CVD is use of sputtering for the film deposition, which is conducted by the sputtering of the Cu based alloy interconnection material followed by reflowing at a high temperature and a high pressure. This reflowing at a high temperature and a high pressure comprises the steps of forming a thin film 5 of a Cu based metal on the surface of an insulator film 2 which is preliminarily formed with a plurality of grooves such as vias (connection holes) 3 or trenches (trenches) 6 by sputtering so that the thin film 5 bridges across the grooves as shown in FIG. 1A; and applying an isotropic pressure in the perpendicular direction to the surface of the thin film (for example, by applying a hydrostatic pressure which is higher than the atmospheric pressure as described in Patent Document 2) as shown in FIG. 1B to thereby force the Cu based metal into the interior of the grooves.
For example, Patent Document 3 proposes formation of an interconnection film by covering the surface of a substrate having deposited thereon an insulator film which is formed with holes or trenches with a metal such as copper, a copper alloy, silver or a silver alloy; and annealing the substrate to thereby fill the holes or the trenches with the metal.
This method still suffers from the problems, for example, that the Cu alloy thin film will not be fully filled in the groove even if the reflowing at a high temperature and a high pressure were carried out if the thin film of Cu alloy formed were not continuous and gas tight, and that the thin film will no longer be filled in the groove once the thin film of the Cu based metal becomes deformed and ruptured. The Cu based thin film formed by sputtering, however, is inferior in reflowability (high temperature flowability) compared to the Cu based thin film formed by electroplating, and improvement of the reflowability during the high-pressure annealing process of the Cu based thin film formed by sputtering has become an important challenge in employing the damascene interconnection technique.
In addition, when the high temperature flowability of the Cu based thin film formed by sputtering is insufficient, or when the Cu based thin film is to be fully filled in a via or a trench having a minute diameter or width and a high aspect ratio, an even higher temperature and pressure are required. However, realization of such temperature and such pressure is difficult under present technology, and even if realization of such conditions were possible, treatment under such high temperature and such pressure is associated with certain danger. Accordingly, filling of the Cu based thin film under a milder condition is highly required.
[Patent Document 1] Japanese Unexamined Patent Application No. H10-79428
[Patent Document 2] Japanese Unexamined Patent Application No. H5-211238
[Patent Document 3] Japanese Unexamined Patent Application No. 2001-7050